To obtain the most likely code with simple configuration by limiting possible state transitions of an input signal according to a corrected temporary discrimination result, detecting the most probable state transition from among the limited transitions, and outputting the discrimination result of the input signal.

An isolated waveform detecting circuit of a temporary discriminator 22 sequentially latches a binary signal S2 in timing a 1/2 clock cycle off the timing of the generation of a temporary discrimination result, and then an AND circuit decides the logical level of the latch result of three successive clocks. Consequently, a temporary discrimination result D3 which is inverted in logical level from a regenerated signal RF for a period of one clock is outputted from a gate circuit. A most likelihood decoder 23 limits the possible state transitions of a digital regenerated signal DRF, generated by a regenerating equalizer 25, according to the temporary discrimination result D3, and the most probable state transition is detected from among the limited state transition to generate a discrimination result D1.