PURPOSE: To improve the stability and reliability of data reproduction by synthesizing two pieces of data with respect to the output of a dual PLL discriminating circuit, thereby increasing the slicing level margin at the time of data reproduction.

CONSTITUTION: An RS counter 44 counts RS with the result of detection of a sync detecting circuit 42 and clock and applies the RS to an RS circuit 45 which detects the RS and applies the RS to an S/P conversion circuit 46. As a result, a decoder 43 subjects the data from a shift register 41 to decoding by the clock and applies the data to the circuit 46. The circuit 46 converts the decoded serial data to parallel data by the detection results of the circuits 42, 45 and applies the data to a semiconductor chip 20. Namely, the data independently have two pieces of the PLLs transmitted at the same frequency and, therefore, if the clock of the PLLs slips, the synthesized phase slips as well and this deviation is detected by the RS. The deviation is prevented by resynchronizing the synthesized phase of the VFO circuits 13, 14, the decoder 32 and the circuit 46.