To reduce the phase error in the case that both clock signals are in matching with each other.

An external clock CLKSYS becomes an internal clock CLKFB via a delay circuit 21 and a clock buffer 22. A phase comparator 23 detects a phase difference of both the clock signals. A counter 24 changes a count (address) based on a comparison result of the phase comparator 23. A least significant bit of the count is used to control on/off of gates 27-0, 27-1. Other bits than the least significant bit in the count are given to a decoder 25. An output of the decoder 25 is used to control on/off of gates 26-0 to 26-(N-l). Furthermore, a change in a delay of the delay circuit 21 is not constant and includes in the vicinity of a phase difference not detected by the phase comparator.