To provide a design method for a semiconductor integrated circuit capable of reducing peak power of the semiconductor integrated circuit without increasing the number of buffers.

A design method for a semiconductor integrated circuit according to the invention includes: a step for dividing an arrangement region into multiple regions; a step for calculating an initial value of delay margin between each clock element that is arranged in the regions; a step for setting a relative delay target value to each of the regions; a step for allocating a relative delay value to each clock element so as to approach to the relative delay target value set to each of the regions; a step for generating clusters including the clock elements, based on a location of each clock element and the relative delay value allocated to each clock element; a step for inserting a buffer into each cluster; a step for allocating a value, which is based on the relative delay value allocated to each clock element included in the clusters, to the buffer; and a step for executing wiring of the buffer so as to satisfy the value based on the relative delay value allocated to the buffer.