To provide a method and a device for specifying quickly a trouble portion proposed of a conbinational logic circuit given, and capable of enhancing precision.

This device is provided with a data receiving part 1 for receiving a test pattern data 8 and a simulation data 7 to be sorted, a normal-pattern- time data analyzing part 3 for specifying a trouble portion proposed according to a trouble portion determining condition in which a relationship among an offset logical value, a logic gate classification with a net connected to an input terminal, and a net degenerate trouble is specified based on the offset logical value and the logic gate classification with the net connected to the input terminal, when the fact that the logical value of the net is offset to a certain value is detected by aquiring the simulation data 7 at the time of a normal test pattern output to investigate a transition of the logical value of the each net in a logic circuit based on the simulation data, and a proposed-trouble outputting means 5 for outputting proposed-trouble information specified in the data analyzing part 3.