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Patent Searching and Data


Title:
DEVICE AND METHOD FOR FAULT SIMULATION AND COMPUTER- READABLE RECORDING MEDIUM STORING FAULT SIMULATION PROGRAM
Document Type and Number:
Japanese Patent JP2001092873
Kind Code:
A
Abstract:

To provide a fault simulation method by which processing time can be shortened.

The fault simulation method includes at least a step of calculating code coverage of test patterns to functional blocks, a step of preparing a list indicating relation among the test patterns, the functional blocks, and their internal nodes, and a step of preparing fault assuming information which assumes faults only for the functional blocks for which RTL codes are executed and their internal nodes. The method also includes at least a step of executing fault simulation for a test pattern on fault-assumed nodes for which the faults are assumed in the order of the code coverage, a step of preparing fault dictionaries on which fault-detected codes from which the faults are detected and a fault recognition rate of the test pattern are described, and a step of removing the overlapping fault-detected nodes from the fault-assumed nodes of the test pattern on which the fault simulation is not executed. In addition, the method also includes at least a step of calculating the total fault recognition rate by combining the fault dictionaries.


Inventors:
KAMITOSA YASUSHI
Application Number:
JP27127899A
Publication Date:
April 06, 2001
Filing Date:
September 24, 1999
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G01R31/3183; G06F11/22; G06F11/26; G06F17/50; G01R31/28; (IPC1-7): G06F17/50; G01R31/28; G06F11/22
Attorney, Agent or Firm:
Hidekazu Miyoshi (7 outside)