PURPOSE: To sufficiently reduce a waiting time in a device for operating a multiprocessor system in which each processor can be connected with a common bus system in a correct priority order by a bus arbiter and a bus connecting element controlled by this.

CONSTITUTION: This device is provided with circuit means U1 and U2 for registering a waiting time T4 of processors P2 and P3 generated at the time of each arbitration. Also, this device is provided with means Z1 and Z2 for delaying the bus access demand of the processors P2 and P3 having a waiting duty, and the delay time T4 of the means Z1 and Z2 is set to be equivalent to at least the previously registered waiting time.