Title:
処理回路素子に対するトリガ信号のアサーションを制御する装置及び方法
Document Type and Number:
Japanese Patent JP7026107
Kind Code:
B2
Abstract:
An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being notified to the trigger signal generation circuitry. This allows the monitoring of particular program instruction execution behaviour to be qualified so that the processing circuitry is only notified if in addition a qualifying event is determined to be present.
Inventors:
Botman, Francois Christopher Jack
Grocat, Thomas Christopher
Holy, John Michael
Williams, Michael John
Grocat, Thomas Christopher
Holy, John Michael
Williams, Michael John
Application Number:
JP2019510437A
Publication Date:
February 25, 2022
Filing Date:
August 10, 2017
Export Citation:
Assignee:
Arm limited
International Classes:
G06F11/36; G06F11/34; G06F15/78
Domestic Patent References:
| JP2005317023A | ||||
| JP9319607A | ||||
| JP7095316B2 | ||||
| JP2000181746A | ||||
| JP2007257441A | ||||
| JP2004178590A |
Attorney, Agent or Firm:
Asamura patent office