Title:
デジタル位相制御方法及びデジタル位相制御回路
Document Type and Number:
Japanese Patent JP4454810
Kind Code:
B2
Abstract:
A digital phase control method phase shifts a predetermined number of clock signals having the same frequency and having different phases at high precision and at high resolution as a whole with its phase interval maintained to keep a predetermined interval. The digital phase control method comprises the steps of preparing fourteen first multi-phase clock signals having a fixed phase, of preparing sixteen second multi-phase clock signals, of phase locking a specific clock signal of the fourteen first multi-phase clock signals with a particular clock signal of the sixteen second multi-phase clock signals, and of changing a combination of the specific and the particular clock signals to be phase-locked to phase shift the second multi-phase clock signals. In addition, in order to generate the second multi-phase clock signals, a delay line comprising ring-shaped chained delay buffers may be used.
More Like This:
| JP2004180125 | SEMICONDUCTOR DEVICE |
| JPH11143574 | CLOCK GENERATION CIRCUIT AND CLOCK GENERATION METHOD |
Inventors:
Satoshi Nakamura
Application Number:
JP2000237458A
Publication Date:
April 21, 2010
Filing Date:
August 04, 2000
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
G06F1/06; H03L7/081; G06F1/10; H03K5/04; H03L7/00; H03L7/07; H03L7/083; H03L7/099; H04L7/033; H03L7/089
Domestic Patent References:
| JP10276074A | ||||
| JP11261388A |
Attorney, Agent or Firm:
Aperture Muneaki