Title:
DIGITAL PHASE LOCK LOOP BEING MADE NESTING
Document Type and Number:
Japanese Patent JPH08237118
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To maintain synchronization to suppress the occurrence of silence by making phases of generated restoring clocks A and B coincide with each other at the time of alteration of output data in narrow and wide band width DPLLs which perform center bit sampling of the restored data. SOLUTION: Narrow and wide band width DPLLs 402 and 404 use filters 4141 and 432 to generate restored clocks (CK) 410 and 428. At this time, filters output adjustment signals 416 and 434 by signals 412 and 430 which phase detectors 408 and 426 output based on phases of restored data 406 and CKs 410 and 428. Phase adjustment circuits 418 and 436 which use these adjustment signals make phases of CKs coincide with each other by an output signal 422 of a VCO 420, the CK 410, and the detection signal of a signal quality detector 444. After initialization/stabilization of a PLL 402, an FF 438 outputs data 440, which is obtained by sampling center data of data 406, by using the CK 410 or 428 selected by a multiplexer 424. Thus, synchronization is maintained to suppress the occurrence of silence.
Inventors:
POORU DEII MAAKO
KUREIGU PII UEIDEN
DEEBITSUDO ERU BURAUN
KUREIGU PII UEIDEN
DEEBITSUDO ERU BURAUN
Application Number:
JP27513095A
Publication Date:
September 13, 1996
Filing Date:
September 29, 1995
Export Citation:
Assignee:
MOTOROLA INC
International Classes:
H03L7/06; H03L7/07; H03L7/099; H04L7/033; H04L7/00; (IPC1-7): H03L7/06; H04L7/033
Attorney, Agent or Firm:
Masanori Honjo (1 person outside)