To provide a digital PLL circuit whose lick-up time is speeded up.

An error between signals outputted from the sampling circuit 6 and 9 in input signals from a reference signal and the output of a variable frequency divider, which is obtained by frequency-dividing a signal from a voltage controlled oscillator 4, is repetitively compared. When the error is large, a time constant for a digital filter 7 is set to a small value. When the error becomes small, the time constant is set to a large value. Then, lock-time is shortened and spurious radiation is suppressed.