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Title:
DISPLAY PANEL, ITS DRIVING METHOD AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2008304945
Kind Code:
A
Abstract:

To suppress voltage-drop/signal-delay without damaging display properties.

An EL display panel 1 is equipped with: an insulating substrate 2; driving transistors 23 arranged in a matrix on the insulating substrate 2; signal lines Y1 to Yn patterned with a gate 23g of the driving transistor 23 and arranged parallel to one another; a protective insulating film 32 covering the signal lines Y1 to Yn and the driving transistors 23; a pixel electrode 20a electrically connected to the drain 23d of each driving transistor 23; an organic EL layer 20b formed on each pixel electrode 20a; a counter electrode 20c covering the organic EL layer 20b; and a feeder line 90 formed on the protective insulating film 32 to be parallel to the signal lines Y1 to Yn between adjacent pixel electrodes 20a, and connected to the source 23s of the driving transistor 23 through a contact hole 53 formed in the protective insulating film 32.


Inventors:
SHIRASAKI TOMOYUKI
OGURA JUN
KUMAGAI MINORU
Application Number:
JP2008231811A
Publication Date:
December 18, 2008
Filing Date:
September 10, 2008
Export Citation:
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Assignee:
CASIO COMPUTER CO LTD
International Classes:
G09F9/30; H01L27/32; H01L51/50; H05B33/06; H05B33/10; H05B33/12; H05B33/22; H05B33/26
Domestic Patent References:
JP2002372921A2002-12-26
JP3551194B12004-08-04
JP2004127933A2004-04-22
JP2003178874A2003-06-27
JPH11329741A1999-11-30
JP2004139879A2004-05-13



 
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