To provide a duty correction circuit without a problem caused in a conventional circuit such as the occurrence of dispersion in an output clock duty due to dispersion in the capacitance of a capacitor.

This circuit is provided with a clock generating circuit 10 outputting clock (h) whose duty is variable, and a control circuit 20 controlling the clock generating circuit 10. The clock generating circuit 10 uses a leading edge phase of an input clock (a) for a leading edge phase of the generated output clock (h) and uses a trailing edge phase controlled by the control circuit 20. The control circuit 20 generates a control signal (b) relating to the trailing edge phase of the clock generating circuit 10 by delaying the input clock (a) with 1st and 2nd variable delay circuit 21, 22.