LEVEL CONVERSION CIRCUIT

Title:

LEVEL CONVERSION CIRCUIT

Document Type and Number:

Japanese Patent JPH09200004

Kind Code:

A

Abstract:

To provide a level conversion circuit capable of being operated at a high speed even under the operation at a low power supply voltage.

This circuit is roughly constituted of an emitter follower section 101, an amplitude extension section 102 and a level conversion section 103. In the amplitude extension section 102, a gate of an N-channel MOS transistor(TR) M1 is connected to a nose 001, a connection node 002 of a drain is connected to a high level power supply terminal VCC and a source is connected to a node 004. Then a base of an N-channel MOS TR M2 is connected to a reference power supply terminal VR, a drain connection node 003 is connected to the high level power supply terminal VCC via a resistor R3 and a source connects to the node 004. Then a base of an NPN TR Q4 is connected to a reference power supply terminal VCSI, a collector is connected to the node 004 and an emitter is connected to a 1st low level power supply terminal GND1 via a resistor R4.

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Inventors:

SUGANO HIROSHI

Application Number:

JP590596A

Publication Date:

July 31, 1997

Filing Date:

January 17, 1996

Export Citation:

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Assignee:

NEC CORP

International Classes:

H03K5/003; H03F3/45; H03K19/017; H03K19/0175; (IPC1-7): H03K5/003; H03F3/45; H03K19/017; H03K19/0175

Attorney, Agent or Firm:

Naoki Kyomoto (2 outside)

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