Title:
MULTIPLIER
Document Type and Number:
Japanese Patent JP3153370
Kind Code:
B2
Abstract:
PURPOSE: To provide a multiplier which can execute multiplication at high speed with the small number of elements.
CONSTITUTION: Code inverse booth encoders 51 and 52 included in an encoding circuit 700 generate output signals that conventional booth encoders 1 and 3 generate and a control signal designating a partial product whose code differs from that of output signal which conventional booth encoders 1 and 3 generate. A partial product generation circuit 702 generates the partial product in accordance with a control signal from the encoding circuit 700. Thus, the partial product whose code is inverted is generated from shifter invertor circuits 10 and 12. A conversion circuit 57 generates one ternary redundant binary with the partial product whose code is inverted and the partial product whose code is not inverted as a pair. An intermediate sum generation circuit 59 generates one redundant binary by adding the ternary redundant binary to the redundant binary. A final addition circuit 61 converts one ternary redundant binary which is finally generated into a regular binary and generates the product Z of the binaries X and Y.
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Inventors:
Makino, Hiroyuki
Application Number:
JP496493A
Publication Date:
April 09, 2001
Filing Date:
January 14, 1993
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F7/49; G06F7/48; G06F7/52; G06F7/533; H03M7/04; (IPC1-7): G06F7/52
Attorney, Agent or Firm:
深見 久郎 （外３名）