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Patent Searching and Data


Title:
ELECTRONIC UNIT AND PROCESSING METHOD IN BUS INITIALIZED PHASE FOR INTERFACE DEVICE OF DIGITAL SERIAL DATA
Document Type and Number:
Japanese Patent JP2001292146
Kind Code:
A
Abstract:

To normally operate a short bus resetting, even if a cable with a connection opposite party is long.

In a bus initialized phase, a system is moved to the state (state of R1) of reset start at first and bus reset signals are transmitted to all connection opposite parties during prescribed time (1.26 μs in minimum and 1.40 μs in maximum in short bus resetting) regulated by reset-time. The system is moved to the state (state of R1) of reset waiting after prescribed time passes and the reception of the bus reset signals from all connection opposite parties is recognized. Thus, it is prevented to have an IDLE signal is received from the connection opposite party having the long cable in the state of R1, the system is moved erroneously to a tree identification phase, the bus reset signal is received from the connection opposite party after movement to the tree identification phase and the system returns again to the state of R0 in the bus initialized phase.


Inventors:
OKAWA YOSHIHIRO
MIURA KIYOSHI
Application Number:
JP2000107065A
Publication Date:
October 19, 2001
Filing Date:
April 07, 2000
Export Citation:
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Assignee:
SONY CORP
International Classes:
G06F1/24; G06F13/00; G06F13/38; G06F13/42; H04L29/08; (IPC1-7): H04L12/28; G06F1/24; G06F13/38; H04L29/08
Attorney, Agent or Firm:
Kunio Yamaguchi (1 person outside)