Title:
ENCODER AND A/D CONVERTER
Document Type and Number:
Japanese Patent JP3157778
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce a load capacitance of each bit line by decreasing the number of ROM cells connecting to each bit line of the encoder, to attain high speed operation of the encoder, to reduce the power consumption and to improve the conversion accuracy.
SOLUTION: Between a plurality of the bit lines BL and a plurality of the word lines WL, a plurality of ROM cells 42 are connected to provide an output of a digital output signal Dout corresponding to a word selection signal received by a plurality of word lines WL from a plurality of bit lines BL. A plurality of the word lines WL to select the ROM cells 42 connecting to a same bit line BL are connected to a logic processing circuit 41 and the ROM cells 42 are selected based on an output signal from the logic processing circuit 41.
Inventors:
Tsukamoto Sanroku
Ian Dedic
Kamei Kuniyoshi
Toshiro Endo
Ian Dedic
Kamei Kuniyoshi
Toshiro Endo
Application Number:
JP14909298A
Publication Date:
April 16, 2001
Filing Date:
May 29, 1998
Export Citation:
Assignee:
富士通株式会社
富士通ヴィエルエスアイ株式会社
富士通ヴィエルエスアイ株式会社
International Classes:
H03M1/36; (IPC1-7): H03M1/36
Domestic Patent References:
| JP57204633A | ||||
| JP6444128A | ||||
| JP3250816A | ||||
| JP61270919A |
Attorney, Agent or Firm:
Hironobu Onda