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Title:
EXCEPTIONAL INTERRUPTION PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPS60225943
Kind Code:
A
Abstract:

PURPOSE: To execute a trap processing at a high speed by constituting a titled system so that an address of a task corresponding to a trap factor is obtained from a trap mapping table, by the contents of a trap vector table, with respect to a trap issued at the time of storage.

CONSTITUTION: When a trap of a supervisor call SVC, etc. is generated, in case the contents of a flag register 61 are "1", it is a trap from a secondary OS task 52, therefore, first of all, the contents of a program counter PC and a status register SR are saved to a stack which is being used at present. Thereafter, the contents of a trap mapping table 63 of an address shown by a pointer register 62 are referred to directly without executing a processing for referring to an address of an interruption vector table 51-1, which is executed by a conventional technique. Subsequently, a control shifted directly to an address of a trap processing task corresponding to a trap factor is executed.


Inventors:
TSUTSUI SHIGECHIKA
SUGITA YUMIKO
Application Number:
JP8175784A
Publication Date:
November 11, 1985
Filing Date:
April 25, 1984
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F9/48; G06F9/46; G06F12/10; (IPC1-7): G06F9/46; G06F12/10
Attorney, Agent or Firm:
Akio Takahashi



 
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