PURPOSE: To realize the fault detection for the address bus, by transmitting periodically the specific signal for the test of the address bus to the address bus from CPU and then testing the specific signal through the test circuit.
CONSTITUTION: When CPU transmits the signals of AB0=AB2∼AB14="1" and AB1=AB3∼AB15="0" to address bus AB0-15, the outpts of exclusive logic sum circuit GTO are all "1" along with output A of NAND circuit GT1 turnd to "0" each. And output C of mono-multi M/M to which above-mentioned outputs are supplied turns to "1". Then when CPU transmits the signals of AB0∼AB2∼AB14= "0" and AB1∼AB15="1" to the same bus, the outputs of exclusive logic sum circuit GT2 are all "1". And output B of inverter GT4 turns to "1" via NAND circuit GT3. Accordingly, the output of NAND circuit GT5 turns to "0", and timer circuit TM is reset. Thus the specific signal is transmitted periodically to bus AB0-15 from CPU. As a result, the fault of the bus can be detected in case the output exists in circuit TM.
| JPS59119598 | DUAL STORAGE DEVICE |
| JPH08249133 | METHOD AND SYSTEM FOR FAULT MEASURE OF DISK DRIVE ARRAY |
ISHIBASHI YOSHIJI
ONO TAKAO
YAMAZAKI MASASHI
NIPPON TELEGRAPH & TELEPHONE
FUJITSU LTD
| JPS50105037A | 1975-08-19 | |||
| JPS5324255A | 1978-03-06 |