Title:
FERROELECTRIC MEMORY
Document Type and Number:
Japanese Patent JP2007122874
Kind Code:
A
Abstract:
To reduce an array occupancy area of ferroelectric memory.
Two ferroelectric memory cells (MC) are arranged for every three word lines (WL0-WL5) in the row direction, and two ferroelectric memory cells are arranged for every three bit lines (BL0-BL5) in the column direction. The memory cells are arranged so that the arrangement patterns are shifted by one bit in adjacent rows, and the arrangement patterns are shifted by one bit also in adjacent columns. A bit line pair is selected so that one bit memory cell is connected to the bit pair according to the position of a selected memory cell. The memory cells can be arranged in high density and the array occupancy area can be reduced accordingly.
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Inventors:
HIDAKA HIDETO
Application Number:
JP2007019334A
Publication Date:
May 17, 2007
Filing Date:
January 30, 2007
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
G11C11/22
Domestic Patent References:
| JPH06342597A | 1994-12-13 | |||
| JPH04271086A | 1992-09-28 | |||
| JPH07312079A | 1995-11-28 | |||
| JPH05198161A | 1993-08-06 |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai