Title:
FINITE INPULSE RESPONSE DIGITAL FILTER
Document Type and Number:
Japanese Patent JPS62293811
Kind Code:
A
Abstract:
PURPOSE: To simplify the hardware constitution by switching two serial multipliers to which plural-bit data are supplied in bit serial depending at the period of the output side so as to obtain an output.
CONSTITUTION: The phase of the operation processing priod is made different in the serial multipliers 11-1, 11-2 and the multiplication processing is applied in the overlapping form by a half period each. Then each multiplier applies the operation corresponding to equation of 1+2Z-1 +3Z-2+∼+16Z-16+∼+Z -30. A counter 3 turns on/off a gate corresponding to the multiplier according to the coefficients '1', '2',∼'16', '15'∼'1'. The serial multipliers are utilized in such a way and the hardware constitution is remarkably simplified.
Inventors:
KARIBE HIROHISA
HASEGAWA KENZO
HAYASHI TOSHIO
UCHIMURA KUNIHARU
HASEGAWA KENZO
HAYASHI TOSHIO
UCHIMURA KUNIHARU
Application Number:
JP13703486A
Publication Date:
December 21, 1987
Filing Date:
June 12, 1986
Export Citation:
Assignee:
FUJITSU LTD
NIPPON TELEGRAPH & TELEPHONE
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03H17/06; H03H17/02; (IPC1-7): H03H17/06
Attorney, Agent or Firm:
Yutaka Morita