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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS62293812
Kind Code:
A
Abstract:

PURPOSE: To select one gain freely among plural kinds of gains by forming a switch control signal making a capacitor setting plural kinds of the gains connect selectively by the write into a FAMOS transistor (TR).

CONSTITUTION: Capacitors C, 2C, 4C and 8C are provided between an inverting input (-) and an output terminal (Vout) of an operational amplifier circuit OP via a CMOS switch circuit respectively to set plural kinds of gains. The capacitance of the capacitors is selected in the ratio of 1,2,4 and 8 with respect to the capacitance of the input capacitor C selected as the unity. 15 Ways of gains are provided according to 15 ways of write information to four FAMOS TRs Q18∼Q21. That is, one gain is set optionally among the gains 1∼15 according to the ratio of the capacitance of the input capacitor C to the combined capacitance of the feedback capacitors C∼8C.


Inventors:
HAGIWARA SHIRO
MIYAKE NORIO
Application Number:
JP13591286A
Publication Date:
December 21, 1987
Filing Date:
June 13, 1986
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03H19/00; (IPC1-7): H03H19/00
Attorney, Agent or Firm:
Katsuo Ogawa