PURPOSE: To make software simple and efficient by processing the erase/write procedure of a flash memory and the generation of a parity bit by hardware.

CONSTITUTION: The flash memory is provided with a data memory 3-1 and a parity memory 3-2. In the writing for the flash memory, an MPU 1 outputs an address 101, a status 102, the data 103. A flash memory control circuit 6 generates the parity bit from the data 103, and writes in the parity memory 3-2 through a parity buffer 4-2. Further, the data 103 itself are written in the data memory 3-1 through a data buffer 4-1. The flash memory circuit 6 executes the verification in the writing to return a ready signal 110 to the MPU 1 when the writing is normal. When the writing is abnormal, the circuit 6 turns on an error status to return the ready signal 110.