FLASH MEMORY DEVICE HAVING THREE-DIMENSIONAL STRUCTURE WITH IMPROVED DRIVING SYSTEM, AND METHOD OF DRIVING THE SAME

Japanese Patent JP2008310949

A

To provide a flash memory device capable of improving an integrating degree and performance for driving the device, and a method of driving the same.

This flash memory device is equipped with a plurality of layers each arranged stacked vertically with a plurality of layers includes a plurality of memory cells, and a row decoder which is electrically coupled to the plurality of layers and supplies a wordline voltage to the plurality of layers. The device is characterized in that memory cells provided in at least two layers out of the plurality of layers are set in one block and the wordlines associated with the memory cells provided in at least the two layers are electrically coupled.

JPH11110499	FREQUENCY COUNTER AND FREQUENCY COUNT METHOD
JP4091984	Multi-bit single cell memory with tapered contacts
JP3783152	MULTI-LEVEL NON-VOLATILE SEMICONDUCTOR MEMORY

KIM DOO-GON
PARK KI-TAE
LEE YEONG-TAEK

JP2008153155A

December 25, 2008

June 11, 2008

Click for automatic bibliography generation  

SAMSUNG ELECTRONICS CO LTD

G11C16/02; G11C16/04; G11C16/06; H01L21/8247; H01L27/115; H01L29/788; H01L29/792

JP2008192708A

2008-08-21

JPN6012049756; Ｓｏｏｎ-Ｍｏｏｎ　Ｊｕｎｇ，　ｅｔ　ａｌ: 'Ｔｈｒｅｅ　Ｄｉｍｅｎｓｉｏｎａｌｌｙ　Ｓｔａｃｋｅｄ　ＮＡＮＤ　Ｆｌａｓｈ　Ｍｅｍｏｒｙ　Ｔｅｃｈｎｏｌｏｇｙ　Ｕｓｉｎｇ　Ｓｔａｃｋｉｎｇ　Ｓｉｎｇｌｅ　Ｃｒｙｓｔａｌ　Ｓｉ　Ｌａｙｅｒｓ　ｏｎ' Ｅｌｅｃｔｒｏｎ　Ｄｅｖｉｃｅｓ　Ｍｅｅｔｉｎｇ，　２００６．　ＩＥＤＭ　'０６．　Ｉｎｔｅｒｎａｔｉｏｎａｌ , 20061211, Ｐ．１-４, ＩＥＥＥ
JPN6012049758; Ｋｉ-Ｔａｅ　Ｐａｒｋ，　ｅｔ　ａｌ: 'Ａ　４５ｎｍ　４Ｇｂ　３-Ｄｉｍｅｎｔｉｏｎａｌ　Ｄｏｕｂｌｅ-Ｓｔａｃｋｅｄ　Ｍｕｌｔｉ-ｌｅｖｅｌ　ＮＡＮＤ　Ｆｌａｓｈ　Ｍｅｍｏｒｙ　ｗｉｔｈ　Ｓｈａｒｅｄ　Ｂｉｔｌｉｎｅ　Ｓｔｒｕｃｔｕｒｅ' Ｓｏｌｉｄ-Ｓｔａｔｅ　Ｃｉｒｃｕｉｔｓ　Ｃｏｎｆｅｒｅｎｃｅ，　２００８．　ＩＳＳＣＣ　２００８．　Ｄｉｇｅｓｔ　ｏｆ　Ｔｅｃｈｎｉｃａｌ　Ｐａｐｅｒｓ．　ＩＥＥＥ　Ｉｎｔｅｒｎａｔｉｏｎａｌ , 20080203, Ｐ．５１０，５１１，６３２, ＩＥＥＥ

Makoto Hagiwara

Previous Patent: NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING IT, AND ITS PROGRAMMING METHOD AND READING METHOD

Next Patent: SEMICONDUCTOR PROCESSOR AND IC CARD