PURPOSE: To attain the initial value setting in high speed in constituting a shift register by providing a signal path where it is brought in the through-state from a data input terminal to a data output terminal.

CONSTITUTION: A latch circuit comprising transmission gates 21, 22 and inverters 31, 32 and a latch circuit comprising transmission gates 23, 24 and inverters 33, 34 are controlled by a clock signal from a terminal 11 at the steady-state thereby allowing an input signal from a terminal 10 to be transmitted to a terminal 13. Transmission gates 25, 26 bypasses the transmission gates 21, 23 by receiving a signal from a terminal 12 at the initial value setting so that the input signal is transmitted to the terminal 13 independently of the clock signal. Since the input value to the terminal 10 is transmitted to the final stage as it is in constituting the shift register, the initial value setting is executed in high speed.