Title:
FORMATION OF DUMMY GATE
Document Type and Number:
Japanese Patent JP3157647
Kind Code:
B2
Abstract:
PURPOSE: To provide a dummy gate forming method with which the dummy gate length is obtained as designed by reducing the effect of the standing wave when a resist exposing operation is conducted.
CONSTITUTION: A metal film 32 used for formation of a gate electrode is provided on the base layer in a dummy gate forming method. The first film 34 and the second film 36, having the film thickness with which the reflected light of the light to be exposed conjointly with each other on a resist layer 37 will be suppressed, are successively laminated on the above-mentioned metal film. Besides, a resists layer 37 is provided, and after this resist layer has been exposed through the exposure mask 39, a resist pattern 38 is formed by developing. Moreover, a dummy gate 49 is formed on a part of the second film using the resist pattern as a mask. At this time, among the reflected lights to be exposed on the resist layer, at least the reflected light which is reflected by the second film, the reflected light reflected by the first film passing through the second film, and the reflected light reflected by the metal film passing through the first and the second films are cancelled with each other.
Inventors:
Tomoyuki Ohshima
Application Number:
JP10325093A
Publication Date:
April 16, 2001
Filing Date:
April 28, 1993
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H01L21/28; H01L21/338; H01L29/812; (IPC1-7): H01L21/338; H01L29/812
Domestic Patent References:
| JP63293886A | ||||
| JP5158072A |
Attorney, Agent or Firm:
Takashi Ogaki