To configure the multiplier generating a multiplied frequency synchronously with a phase of a reference clock with only a simple digital circuit.

A delay circuit 1 delays a reference clock one after another and outputs a delay signal for each gate. A phase comparator 2 compares a phase of a delay signal with a phase of a reference clock and outputs a detected value. A divider circuit 3 makes a prescribed calculation, based on the detected value and a required multiple. A selector circuit 4 selects a delay signal and provides an output, based on a calculation value of the divider circuit 3. A multiplier arithmetic circuit 5 takes plural exclusive OR processing between the reference clock and the delay signal selected and outputted by the selector circuit 4. Thus, the multiplied frequency signal synchronously with the phase of an input signal is generated. The multiplier is in operation up to a higher frequency with high stability by configuring the multiplier by a digital circuit in this way.