Title:
GATE AND CMOS STRUCTURE AND MOS STRUCTURE
Document Type and Number:
Japanese Patent JP3944567
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide novel gate, CMOS structure and MOS structure exhibiting excellent low resistivity and controllability.
SOLUTION: The gate is composed of an intermetallic compound semiconductor having a semiconductor band structure and an electric conductivity in the range of 102 and 105 S.m-1 under a state added with no impurity.
Inventors:
Toyohiro Chikyo
Motoharu Imai
Motoharu Imai
Application Number:
JP2002056484A
Publication Date:
July 11, 2007
Filing Date:
March 01, 2002
Export Citation:
Assignee:
National Institute for Materials Science
International Classes:
H01L21/28; H01L29/78; H01L21/8234; H01L21/8238; H01L27/088; H01L27/092; H01L29/423; H01L29/43; H01L29/49; (IPC1-7): H01L29/78; H01L21/28; H01L21/8234; H01L21/8238; H01L27/088; H01L27/092; H01L29/43
Domestic Patent References:
| JP59033875A | ||||
| JP59114868A | ||||
| JP61074371A | ||||
| JP6244136A |
Other References:
Toshiyuki HIRANO et. al.,Electrical resistivities of single-crystalline transition-metal disilicides,journal of Applied physics,米国,American institute of Physics,1990年 7月15日,Vol.68,p.627-633
伊藤隆司、石川元、中村宏昭,VLSIの薄膜技術,日本,丸善株式会社,1986年 9月30日,p.171-175
前田和夫,最新LSIプロセス技術,日本,工業調査会,1988年 4月20日,第4版,p.397、398
伊藤隆司、石川元、中村宏昭,VLSIの薄膜技術,日本,丸善株式会社,1986年 9月30日,p.171-175
前田和夫,最新LSIプロセス技術,日本,工業調査会,1988年 4月20日,第4版,p.397、398
Attorney, Agent or Firm:
Toshio Nishizawa
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