ニューラルネットワークを使用した集積回路フロアプランの生成

Japanese Patent JP7413580

B2

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

JP2023137293	DESIGN PROGRAM, DESIGN METHOD AND DESIGN DEVICE
WO/2021/196574	AUTOMATIC LAYOUT METHOD FOR PAD RING USED FOR OPTIMIZING ELECTROSTATIC DISCHARGING CAPACITY OF CHIP
JP7072136	Design support equipment, design support programs and design support methods

Tian-Min Richard Ho
William hung
Mustafa Nazum Yazgan
Anna Darling Goldie
Jeffrey Adgate Dean
Azalea Milhoseni
Emra Tancer
Ya Wan
Anand Bab

JP2023026457A

January 15, 2024

February 22, 2023

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G06F30/392; G06F30/27; G06N3/02; G06N99/00

JP11306216A
JP2001134551A
JP2004259105A

WO2018234945A1

Yasuhiko Murayama
Shinya Mihiro
Tatsuhiko Abe

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