Title:
容量性負荷のための高効率ドライバ回路
Document Type and Number:
Japanese Patent JP4849430
Kind Code:
B2
Abstract:
A circuit for driving capacitive loads in a highly efficient manner. In one embodiment, a drive portion is connected to at least one end of a capacitive electric load being applied a voltage waveform. The embodiment further comprises a switching circuit portion having its output connected to the above one end of the capacitive load in order to supply a fraction of the overall current demanded by the load. Additionally, a switching circuit and accompanying switching method provide for efficiently supplying peak current to the capacitive load during voltage fluctuation in the voltage waveform. Briefly, the invention is a circuit arrangement aimed at providing a highly efficient drive for the capacitive load, using a combined linear/switching setup and without distorting the quality of the waveform generated across the capacitive load.
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Inventors:
Butterlain, Luke
Gallina, Pietro
Mackerel, Giancarlo
Ginko, Giancarlo
Diazzi, claudio
Pedute, Vittorio
Gallina, Pietro
Mackerel, Giancarlo
Ginko, Giancarlo
Diazzi, claudio
Pedute, Vittorio
Application Number:
JP2002528912A
Publication Date:
January 11, 2012
Filing Date:
September 18, 2001
Export Citation:
Assignee:
STMicroelectronics S.r.l.
International Classes:
H03K17/56; H03K4/94; H03K17/16; H01L41/04; H03K17/00
Domestic Patent References:
| JP2000174606A | 2000-06-23 | |||
| JPH10301530A | 1998-11-13 | |||
| JPS4737057A | ||||
| JPH07321623A | 1995-12-08 |
Attorney, Agent or Firm:
Michiharu Soga
Yutaka Ikeya
Hidetoshi Furukawa
Suzuki Kenchi
Kajinami order
Taizo Shiraishi
Yutaka Ikeya
Hidetoshi Furukawa
Suzuki Kenchi
Kajinami order
Taizo Shiraishi