PURPOSE: To reduce the channel selection time by bringing the state to a forced search state after a prescribed time when a channel selection switch is being depressed to apply high speed search.

CONSTITUTION: When an UP switch 13 is depressed from the state receiving an optional station, an UP-DOWN selection circuit 15 in a channel selection control circuit 30 is set and an UP mode signal 28 is set. Then a timer 10 is set through a gate 12 and the level goes to an H level, a search mode setting circuit 16 is set through a gate 11 and a highest speed frequency (mnf) in the output of a clock generating circuit 7 is selected by a clock switching circuit 8, the result is inputted to gates 17, 18 as a search clock 25, the signal is inputted to a counter 19 via a gate 17 opened by the signal 28 and the tuning voltage 21 being the output is fed to a tuner 2. As the voltage 21 rises, a timer 9 is set to form the forced search tate. When the tuning frequency rises and approaches the station frequency, a synchronizing detection signal 22 is set, the AFT signal 23 shows the S-shaped characteristic and the circuit 6 is set to continue the search state.