To minimize the propagation delay time by giving a clock signal and all output signals of D flip-flop circuits of a preceding stage to an input side of each AND circuit provided respectively for a clock input terminal of each D flip-flop at post-stages except the 1st stage flip-flop and giving the clock signal to a clock input terminal of the 1st stage D flip-flop.

A 1st stage D flip-flop DFF1 and 2nd to 4th stages of D flip-flop circuits DFF2, DFF3, DFF4 in a hexadecimal counter circuit consisting of D flip-flop circuits are connected in cascade, output signals Q1, Q2, Q3, Q4 are respectively outputted from output terminals Q, and the D flip-flop circuits DFF1-DFF4 are connected to a reset signal line RST-S so that each output terminal inverse of Q and an input terminal D are connected and a reset signal RST is given simultaneously to each reset terminal R.