PURPOSE: To execute the two-dimensional sequential filter processing at a high speed by entering each picture element sequentially by a window register section 12 according to the picture raster scanning, reconstituting picture elements in a 3×3 window and giving the result sequentially to a bit deciding section.
CONSTITUTION: The most significant bit ∼ the least significant bit of an input data are fed to window generating circuits 512∼515 while being retarded sequentially by the unit time. The bit deciding section 52 comprises stages 521∼524 of the stage number corresponding to the bit length of the input data and each stage consists of determining circuits of the same structure and a number (9 circuits) equal to number of picture elements in the window. The determining circuit 53 consists of determining circuits 531∼534 of the stage number corresponding to the data bit length of the input data. An output register 54 receives the result of decision by a bit corresponding to each picture element outputted from the decision circuits 531∼534 and applies delay synthesis and then the result of a prescribed sequential filter processing is obtained sequentially simultaneously for 4 bits each.
KOMEICHI MASATOSHI
NAKAGAWA KOYO
MIMA TOSHIYA
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