PURPOSE: To control respective signals individually and easily prevent a bus right conflict at the time of multiple use by making the bus right monitoring input terminal and bus right acquisition display output terminal of the DMAC incorporated peripheral LSI separate and independent.

CONSTITUTION: Two LSIs are connected by bus acknowledge daisy chaining which gives priority to the LSI 1 and when one or both of the bus right request signal BUSREQ1 and BUSREQ2 of the LSI 1 are active, a bus request is sent to a microcomputer. When the bus right acknowledgement signal from the microcomputer becomes active, it is inputted at the bus right acknowledgement input terminal BUSACK1 of the LSI 1 and when the BUSREQ1 is active, the LSI1 acquires the bus right and informs the microcomputer and LSI2 of the bus right acquisition from a terminal BUSYO1. After the LSI1 or LSI2 acquires the bus right, DMA transfer with a memory is started and once the transfer ends, the microcomputer and LSI1 or LSI2 are informed of bus right releasing.