To reduce power consumption and heat generation of a PLL (phase-locked loop) circuit used in an image forming apparatus.
The image forming apparatus 110 forms an image by forming an electrostatic latent image on a photoreceptor 11 with a laser beam, developing the electrostatic latent image with a developer to obtain a developer image, and transferring the developer image to a sheet P. The image forming apparatus includes: a light source 43 which outputs the laser beam for exposing the photoreceptor; a PLL circuit 203 which generates a multiplied clock that is obtained by multiplying a reference clock; a pulse-width modulating circuit 54 which outputs a pulse-width-modulated signal in accordance with image data and the multiplied clock in order to drive the light source; and a CPU 50 which obtains image data to be input to the pulse-width modulating circuit and, when it is unnecessary to output the pulse-width-modulated signal in accordance with the obtained image data, stops a driving of the PLL circuit.
| JPH09183250A | 1997-07-15 | |||
| JP2007152731A | 2007-06-21 | |||
| JP2008260130A | 2008-10-30 | |||
| JP2006334948A | 2006-12-14 | |||
| JP2003170622A | 2003-06-17 | |||
| JP2007130892A | 2007-05-31 |
Shinichi Usui
Takao Ochi
Teruhisa Motomiya
Asahi Shinmitsu
Seiichiro Takahashi
Masami Saito
Katsuhiko Kimura
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