Title:
IMAGE PROCESSING METHOD AND IMAGE PROCESSOR
Document Type and Number:
Japanese Patent JP3238543
Kind Code:
B2
Abstract:
PURPOSE: To reduce a circuit scale, to facilitate the miniaturization and to accurately perform image processing by storing a video signal responding to a clock signal in a storage and performing the signal processing only by using the video signal.
CONSTITUTION: This device is provided with a clock generation circuit 21 outputting the clock signal at each fixed period synchronizing with an inputted burst signal and interrupting the output of the clock signal when the number of clocks arrives at a fixed value after a horizontal synchronizing signal is inputted. The storage 22 inputted with the clock signal from the clock generation circuit 21, the video signal, a vertical synchronizing signal and the horizontal synchronizing signal becomes the state where the video signal is inputted from a head address because of the inputted vertical synchronizing signal, and thereafter, the video signal is stored from the head address successively whenever the clock signal from the clock generation circuit 21 is inputted. Then, the video signal is stored in the storage 22 responding to the clock signal during the fixed number of clocks from the horizontal synchronizing signal among the video signals in one picture, and the signal processing is performed only by using the stored video signal.
Inventors:
Yousuke Izawa
Fue Koichiro
Naoshi Okumura
Fue Koichiro
Naoshi Okumura
Application Number:
JP21965093A
Publication Date:
December 17, 2001
Filing Date:
September 03, 1993
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G09G5/12; G06T1/60; H04N5/04; H04N5/14; H04N9/89; (IPC1-7): G09G5/12; G06T1/60; H04N5/04; H04N5/14; H04N9/89
Domestic Patent References:
| JP5130569A |
Attorney, Agent or Firm:
Akio Miyai