Title:
情報処理システム
Document Type and Number:
Japanese Patent JP5561374
Kind Code:
B2
Abstract:
Access contention for a shared resource (106) is resolved while suppressing power consumption in an information processing system (100). A bus controller (108) using a cache miss detecting unit (119), detects first information that indicates with respect to a CPU (101) and a CPU (102), a cache hit or a cache miss. The bus controller (108) using a high-speed I/O detecting unit (120), detects second information that indicates an activated state or a non-activated state of a DMA controller (103) and a DMA controller (104). The bus controller (108) using a generating unit (123), generates a setting signal based on the first information and the second information.
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Inventors:
Koichiro Yamashita
Hiromasa Yamauchi
Takahisa Suzuki
Yasushi Kurihara
Fumihiko Hayakawa
Hiromasa Yamauchi
Takahisa Suzuki
Yasushi Kurihara
Fumihiko Hayakawa
Application Number:
JP2012544020A
Publication Date:
July 30, 2014
Filing Date:
November 15, 2010
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/08; G06F13/16; G06F13/28
Domestic Patent References:
| JPH11134077A | 1999-05-21 | |||
| JPH11110363A | 1999-04-23 | |||
| JP2003242104A | 2003-08-29 |
Attorney, Agent or Firm:
Akinori Sakai