To provide an input protection circuit which can be made high in its sensitivity and stability by eliminating an operational blank duration influenced by a threshold voltage.

An NMOS transistor 12, whose gate is connected to a node N2, is provided to an input node N1 of an input buffer 2. The node N2 is set at a constant voltage by an NMOS transistor 10 which is connected in series with a reference voltage VSS from an internal power voltage IVCC. This constant voltage is a value higher by a threshold voltage of the NMOS transistor 12 than the reference voltage VSS as a correction level of an input signal. Thus, when a voltage at the node N1 becomes lower than the reference voltage VSS, Vgs of the NMOS transistor 12 immediately exceeds the threshold voltage, whereby the NMOS transistor 12 reacts with it and conducted, so that an external power voltage XVCC is transmitted through channel to the node N1. As a result, the voltage level of the node N1 can be immediately corrected.