Title:
INSPECTION CIRCUIT, ELECTROOPTICAL PANEL AND ELECTRONIC APPLIANCE
Document Type and Number:
Japanese Patent JP2004151345
Kind Code:
A
Abstract:
To reduce the leakage amount of an inspection circuit and to reduce a circuit scale.
Analog switches ASW5-ASW7 are connected between data lines 3-1 - 3-3 and inspection lines T1-T3. In inspection, the analog switches ASW1 and ASW2 are turned on and selection signals SEL and inverted selection signals SELX are supplied to the control terminals of the analog switches ASW5-ASW7. In non-inspection, while the analog switches ASW1 and ASW2 are turned off, since the control terminals of the analog switches ASW5-ASW7 are connected through the analog switches ASW3 and ASW4 to a high potential power source VDD or a low potential power source VSS, the analog switches ASW5-ASW7 are surely turned off.
Inventors:
FUJIKAWA SHINSUKE
Application Number:
JP2002316087A
Publication Date:
May 27, 2004
Filing Date:
October 30, 2002
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
G02F1/13; G02F1/133; G09G3/20; (IPC1-7): G09G3/20; G02F1/13; G02F1/133
Attorney, Agent or Firm:
Masahiko Ueyanagi
Fujitsuna Hideyoshi
Osamu Suzawa
Fujitsuna Hideyoshi
Osamu Suzawa