PURPOSE: To reduce the number of input and output pins of an integrated circuit by outputting sequentially signal outputted from a 1st integrated circuit to a 2nd integrated circuit and a signal being the result of retarding the output signal at every cycle with a flip-flop sequentially to a prescribed signal line.

CONSTITUTION: Either of two signals 101-1, 101-2 varies at every 2 cycles is selected sequentially in time series at every cycle at the selection circuit 11 of an integrated circuit 1 and outputted to an integrated circuit 2. Then a signal 201-1 from an input pin 23 of the integrated circuit 2 and an output signal 201-1 from a FF 22-1 retarding the signal 201-1 by one cycle at the FF 22-1 are restored to the signals 101-1, 101-2 of the integrated circuit 1 by using a selection circuit 21. Thus, an output pin 12 is shared in the integrated circuit 1 and the input pin 23 of the integrated circuit 2 is shared. Thus, the number of input and output pins of the integrated circuits 1, 2 sending/receiving the input and output signals mutually is saved.