PURPOSE: To attain miniaturization of a circuit and systolic array formation and to simplify the control by repeating (m-1) times the operation of multiplying an element (x) by a finite element (x) and squaring the product, and calculating an inverse element x-1.

CONSTITUTION: The element is inputted in 4-bit parallel from an input terminal 101 and fed to a square circuit 102. An input inputted from the input terminal 101 and an output x2 from the square circuit 102 are fed to an (M-0) multiplier 103, from which a product x3 is obtained and fed to a square circuit 104. The element (x) retarded by a delay circuit 105 and an output x6 of the square circuit 104 are fed to an M-0 multiplier 106, from which a product x7 is obtained and fed to a square circuit 107. A value x14=x-1 obtained from the square circuit 107 is outputted in 4-bit parallel from an output terminal 108. In general, the inverse element circuit of a GF(2m) in normal base expression consists of (m-2) sets of (M-0) multipliers and (m-1) sets of square circuits.