Title:
JIG FOR MEASURING SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JP2768310
Kind Code:
B2
Abstract:
PURPOSE: To provide a semiconductor wafer-measuring jig which can inspect many semiconductor wafers in a short time at low costs with high frequency waves.
CONSTITUTION: The jig is constituted of a multilayer substrate 2 having a pitch conversion function in which corresponding contacts are different in position at a front and a rear faces by an internal wiring, a plurality of LSI test chips 3 having a part or the total of a test function for testing semiconductor wafers and mounted at one face of the multilayer substrate 2, and a contact film 4 having a plurality of bumps 5, 5' at a front and rear faces of a rubber film base to be connected respectively with a wafer 6 to be measured and the multilayer substrate 2. The front and rear corresponding bumps of the contact film 4 are connected by a surface wiring and an internal wiring.
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Inventors:
Yasushima Masayuki
Nakaizumi Kazuo
Nakaizumi Kazuo
Application Number:
JP12977295A
Publication Date:
June 25, 1998
Filing Date:
April 28, 1995
Export Citation:
Assignee:
NEC
International Classes:
G01R31/26; G01R1/073; H01L21/66; (IPC1-7): G01R1/073; G01R31/26; H01L21/66
Domestic Patent References:
| JP6116519A | ||||
| JP61179747U |
Attorney, Agent or Firm:
Asato Kato