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Patent Searching and Data


Title:
LAYOUT VERIFICATION PROGRAM, LAYOUT VERIFICATION DEVICE AND LAYOUT VERIFICATION METHOD
Document Type and Number:
Japanese Patent JP2013200710
Kind Code:
A
Abstract:

To solve a problem in a conventional layout verification method capable of identifying wiring having short circuit, that it is difficult to identify a location of the short circuit on the wiring having the short circuit.

A layout verification program, a layout verification device, and a layout verification method are configured to: compare a location of a second connection terminal extracted from actual layout information and a location of a first connection terminal previously defined as an inter-hierarchy connection terminal in a lower hierarchy circuit; and output short circuit candidate location information on a wiring pattern according to difference information between the first connection terminal and the second connection terminal.


Inventors:
FUKUNAGA TAKESHI
Application Number:
JP2012068680A
Publication Date:
October 03, 2013
Filing Date:
March 26, 2012
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
G06F17/50
Attorney, Agent or Firm:
Ken Ieiri