To prevent display abnormality from occurring due to parasitic capacitance, and also to form a contact hole highly reliable in electric connection, in a CF on TFT structure using the wiring on a TFT substrate also as BM for a high aperture ratio and high definition.

Parasitic capacitance between a wiring metallic layer such as source wiring 1 and gate wiring 2 and an pixel electrode 6 is reduced by forming a transparent resin layer on a CF layer 9 so that a total thickness of the CF layer and the transparent resin layer is 3 μm to 6 μm. Electric connection at the contact hole is secured by making the contact hole 7b of the transparent resin layer larger than the contact hole 7b of the CF layer by 3μm or more, and making the cross-section of the contact hole 7 in a two-step slope form.