Title:
LOGIC DIVISION DEVICE
Document Type and Number:
Japanese Patent JP3184420
Kind Code:
B2
Abstract:
PURPOSE: To provide a logic division device where design efficiency is improved at the time of allocating the electronic circuits of largescaled ASIC or a logic device into plural programmable chips and an operation can be executed at desired timing.
CONSTITUTION: A logic division processing part 1 dividing the electronic circuit into plural groups and automatically allocating them to the plural programmable chips, a designation file 2 storing input information an ASIC net list file 3 and net list files 4-6 storing output information are provided for the logic division device. The logic division processing part 1 is provided with a judgement part 8 judging whether designated logic block groups can be settled in one programmable chip or not and a division processing part 9 deciding the logic block groups from a higher order in accordance with information on allocation priority and executing a division processing.
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Inventors:
Toshio Oguma
Osamu Tada
Osamu Tada
Application Number:
JP673595A
Publication Date:
July 09, 2001
Filing Date:
January 19, 1995
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP2291080A |
Other References:
山田一久、外３名，”マルチＦＰＧＡシステムによる通信用回路エミュレーションの検討”，電子情報通信学会技術研究報告（ＣＳ９２−７７〜８４），平成５年１月２１日，第９２巻，第４２９号，ｐ．４９−５６
Attorney, Agent or Firm:
Yamato Tsutsui