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Title:
MANUFACTURE OF GAAS SCHOTTKY GATE TYPE FIELD-EFFECT TYPE TRANSISTOR
Document Type and Number:
Japanese Patent JPS6179264
Kind Code:
A
Abstract:

PURPOSE: To form a shallow operating layer having high surface impurity concentration more uniformly with excellent reproducibility, and to obtain a GaAs IC operating at high speed by previously etching the whole surface of a GaAs substrate containing the operating layer or a portion thereof.

CONSTITUTION: Si ions are implanted to a semi-insulating GaAs substrate 21 by using a mask 22, thermally treated, and activated, and CV are measured while employing Al an electrode and the distribution of impurity concentration is investigated. The Al electrode is removed, and the substrate 21 is etched through RIE up to predetermined thickness by using Cl2+BCl3 so as to obtain the desired threshold voltage of a FET. A WN gate electrode 24 is shaped selectively, Si ions are implanted to a source 25 and a drain 26 through self- alignment, the surface is coated with PSG27, and Si ions are annealed and activated. Ohmic electrodes 28 consisting of AuGe/Au are attached to the source and the drain, and thermally treated. According to the constitution, the FET having high gm can be formed uniformly in a wafer surface with excellent reproducibility, and the method is fitted for manufacturing a MESFET for a GaAsIC.


Inventors:
KITAURA YOSHIAKI
UCHITOMI NAOTAKA
HOJO AKIMICHI
Application Number:
JP20063984A
Publication Date:
April 22, 1986
Filing Date:
September 27, 1984
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/338; H01L29/812; (IPC1-7): H01L29/80
Attorney, Agent or Firm:
Noriyuki Noriyuki