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Title:
MANUFACTURE OF HYBRID INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS6070754
Kind Code:
A
Abstract:

PURPOSE: To reduce the occupying area of a thick-film capacitor, and to increase the density of a hybrid integrated circuit and miniaturize the circuit by forming a lower electrode on an insulating substrate and forming a first dielectric layer, a common electrode, a second dielectric layer and an upper electrode on the lower electrode in succession.

CONSTITUTION: A lower electrode 12 is printed and baked on an insulating substrate 11, a first dielectric layer 13 is shaped on the lower electrode, and a common electrode 14 is formed on the dielectric layer 13. The lower electrode 12 and the common electrode 14 are separated electrically by the dielectric layer 13 at that time. A second dielectric layer 15 is formed on the common electrode 14, and an upper electrode 16 is shaped on the second dielectric layer 15. The common electrode 14 and the upper electrode 16 are also separated electrically by the dielectric layer 15 at that time. When each electrode and dielectric layer is superposed and formed on the insulating substrate 11 in mentioned-above order, a capacitor 11 is constituted by the lower electrode 12, the first dielectric layer 13 and the common electrode 14, and a capacitor 12 is constituted by the common electrode 14, the second dielectric layer 15 and the upper electrode 16.


Inventors:
TANAHASHI KAZUOKI
HACHIDAN HIDEAKI
HORIIKE SUMIO
NAKANO HIROYUKI
Application Number:
JP17995583A
Publication Date:
April 22, 1985
Filing Date:
September 27, 1983
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
H01L27/01; H01G4/40; H05K1/16; (IPC1-7): H01G4/40; H01L27/01
Attorney, Agent or Firm:
Nakamura Shigenobu



 
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