Title:
貫通構造を有する薄膜化回路基板の製造方法と保護用粘着テープ
Document Type and Number:
Japanese Patent JP4234630
Kind Code:
B2
Abstract:
A method of manufacturing a thin-film circuit substrate, containing: (a) gouging a surface of a circuit substrate in a depth at least approximately equal to a thickness of a final product of the substrate, to form a section to be formed a penetrating section; (b) providing a protecting adhesive tape to adhere to the gouged surface of the substrate, before a backing surface of the substrate is ground; (c) grinding the backing surface in such a thickness that the gouged section would not penetrate; (d) dry etching entirely the backing surface, while the tape adheres to the substrate, after completion of the grinding for the backing surface; and (e) making the gouged section of the substrate to penetrate, by the dry etching, thereby forming the penetrating structure section; and,
a protecting adhesive tape usable in the method.
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| JPS55164460 | SURFACE GRINDER |
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Inventors:
Shinichi Ishiwata
Inada Masakatsu
Inada Masakatsu
Application Number:
JP2004106510A
Publication Date:
March 04, 2009
Filing Date:
March 31, 2004
Export Citation:
Assignee:
THE FURUKAW ELECTRIC CO.,LTD.
International Classes:
B24B7/22; H01L21/301; B23K26/38; B23K26/40; C09J7/02; C09J7/20; C09J7/38; C09J201/00; H05K3/00
Domestic Patent References:
| JP8020756A | ||||
| JP7106285A | ||||
| JP8330257A | ||||
| JP2002319554A | ||||
| JP2003007649A | ||||
| JP2003007648A | ||||
| JP2002075942A | ||||
| JP2000294522A | ||||
| JP2001210701A | ||||
| JP2000038556A |
Attorney, Agent or Firm:
Toshizo Iida