Title:
MASTER-SLAVE D-TYPE FLIP-FLOP
Document Type and Number:
Japanese Patent JPH01284011
Kind Code:
A
Abstract:
PURPOSE: To generate the separation of a threshold value between a master part and a slave part in a flip-flop by using a duplex emitter transistor inside a pair of master clock differential transistors and a pair of slave clock differential transistors. CONSTITUTION: A master slave D-type flip-flop is provided with the master part 14 providing the pair of master clock differential transistors which are formed by an input transistor MQ14, and a reference transistor MQ13 where an emitter is commonly connected and the slave part 16 providing the pair of slave clock differential transistors which are formed by the input transistor SQ9 and the reference transistor SQ10 where the emitter is commonly connected. The bases of MQ13 and SQ10 are connected, so as to receive a threshold value voltage level VBI which is set intermediately between the logical variabilities of a clock input signal, and the threshold value voltage levels inside the pair of master clock differential transistors and inside the pair of the slave clock differential transistors are off-set.
Inventors:
JIYON CHIYAARUZU BAJIRU
DONARUDO GAADOHAMU GODAADO
DONARUDO GAADOHAMU GODAADO
Application Number:
JP1094389A
Publication Date:
November 15, 1989
Filing Date:
January 18, 1989
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC
International Classes:
H03K3/289; (IPC1-7): H03K3/289
Attorney, Agent or Firm:
Fukami Hisaro (2 outside)