Title:
MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3517946
Kind Code:
B2
Abstract:
PURPOSE: To eliminate the need of precisely managing write timing as against a memory means and to easily conduct the write processing of multiple amount of data.
CONSTITUTION: An address signal and a signal SLB in RAM 3 are formed by counters 10 and 11 from a clock signal CK, horizontal synchronizing signals HD and XHD and a vertical synchronizing signal VD. When a signal SLD based on the signal SLB is 'L', the address signals from the counters 10 and 11 are supplied to RAM 3 through a switch 12. A data signal which is read from RAM 3 is supplied to a shift register 25 and it is fetched when the signal SLD is 'L'. Then, it is converted into serial data and is outputted as a sequential picture switch signal SC. When the signal SLD is 'H', the address signal from a microcomputer 1 is supplied to RAM 3. When a signal SDE is 'H' and a signal SWE is 'H', the data signal is fetched into the microcomputer 1. When the signal SLD is 'H' and the signal SWE is 'L', data is written into the address of RAM 3, which is designated by the address signal of the microcomputer 1.
Inventors:
Motohashi, Toshiharu
Application Number:
JP9517794A
Publication Date:
April 12, 2004
Filing Date:
May 09, 1994
Export Citation:
Assignee:
SONY CORP
International Classes:
G06F12/00; H04N5/278; (IPC1-7): H04N5/278; G06F12/00
Attorney, Agent or Firm:
山口 邦夫 （外１名）
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